Digital demodulator

ABSTRACT

A digital demodulator that eliminates the need for an absolute phase circuit is provided. In a digital demodulator for a digital broadcasting receiver that receives digital time-division multiplexed signals of different types of modulation, the demodulated baseband signal is selectively inverted by an inverter ( 7 ) according to an inversion command signal “0” or “1” that is output from an inversion decision circuit ( 6 ) depending on a BPSK signal of a known pattern. A phase error detector ( 8 ) for carrier reproduction determines the phase error voltage based on the phase difference between the absolute phase and the phase of the signal point of the demodulated baseband signal output from the inverter ( 7 ). The phase error voltage is passed through a carrier filter ( 9 ), including a low-pass filter, to control the carrier frequency so that carrier reproduction can be carried out with the phase at the signal point being coincident with the point of phase convergence.

TECHNICAL FIELD

The present invention relates to a digital demodulator used with adigital broadcasting receiver for receiving BS digital broadcastingprograms, and more particularly to a digital demodulator used with adigital broadcasting receiver for receiving time-multiplexed waves whichwere digitally modulated by a plurality of modulation methods havingdifferent necessary C/N (a ratio of carrier power to noise power)values.

BACKGROUND ART

In a BS digital broadcasting method, a hierarchical transmission methodof repetitively transmitting, one frame after another, time-multiplexeddigital main signals which were modulated by a plurality of modulationmethods having different necessary C/N values, such as 8PSK modulatedwaves, QPSK modulated waves, and BPSK modulated waves, in addition toburst symbol signals inserted in the main signals and capable of beingreceived at a low C/N value. The burst symbol signal is a signal whichwas BPSK modulated by a known PN code.

In such a hierarchical transmission method, a frame sync pattern and asuperframe identification signal have predetermined patterns which wereBPSK modulated. A digital demodulator of a digital broadcasting receiverperforms absolute phasing which makes the reception phase be coincidentwith the transmission phase, in order to decode the demodulated basebandsignal by a decoder or to perform other operations. In the hierarchicaltransmission method, a frame sync signal, a TMCC signal for transmissionand multiplexing configuration control to be described later and a burstsymbol signal are BPSK demodulated, and the absolute phasing isperformed in accordance with the reception phase of the received framesync pattern (absolute phase reception, inverse phase reception).

However, a necessary circuit area of an integrated digital demodulatorbecomes large because of the presence of an absolute phasing circuit.

An object of the invention is to provide a digital demodulator whichdoes not require an absolute phasing circuit.

DISCLOSURE OF THE INVENTION

The invention provides a digital demodulator for a digital broadcastingreceiver for receiving digital modulated waves multiplexed in time axisby a plurality of modulation methods, comprising:

inverter means for selectively inverting demodulated baseband signals inaccordance with a BPSK signal having a known pattern prepared inadvance; and

carrier reproduction phase error detector means provided with a phaseerror table having a phase converging point as an absolute phase, thecarrier reproduction phase error detector means outputting a phase errorsignal corresponding to a phase difference between a phase obtained froma signal point of the demodulated baseband signals output from theinverter means and a phase of the phase converging point,

wherein carrier reproduction is executed by controlling a frequency of areproduction carrier so as to make the phase of the signal point becomecoincident with the phase converging point.

According to the digital demodulator of this invention, the demodulatedbaseband signals are selectively inverted in accordance with the phaseof the BPSK signal having the known pattern prepared in advance.Therefore, the reference point of the demodulated baseband signalsselectively inverted takes an absolute phase. The reference point of thedemodulated baseband signals not inverted takes also the absolute phase.The carrier reproduction phase error detector means refers to the phaseerror table, and outputs a phase error signal corresponding to a phasedifference between the phase obtained from a signal point of thedemodulated baseband signals selectively inverted and the phase of thephase converging point of the absolute phase. The carrier reproductionis executed by controlling the frequency of the reproduction carrier soas to make the phase of the signal point become coincident with thephase converging point. The phase point of the reception signal istherefore converged to the absolute phase and the reception signal issubjected to the absolute phasing. An absolute phasing circuit istherefore unnecessary.

The digital demodulator of this invention further comprises the carrierfilter of a low-pass filter, the carrier filter being input with thephase error signal from the carrier reproduction phase error detectormeans and stopping a filtering operation during a TMCC section, and aBPSK signal section, a QPSK signal section and an QPSK signal section ofmain signals, and the carrier reproduction being executed in accordancewith an output of the carrier filter.

The digital demodulator of this invention is provided with the carrierfilter of a low-pass filter whose filtering operation stops during theTMCC section, and the BPSK signal section, a QPSK signal section and an8PSK signal section of the main signals. Although the phases of thedemodulated baseband signals during the BPSK signal section, QPSK signalsection and 8PSK signal section of the main signals are compared withthe absolute phase, the filtering operation of the carrier filter stopsduring these signal sections and any practical problem will not occur.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing the structure of a digital modulatoraccording to an embodiment of the invention.

FIGS. 2(A)-2(G) are a diagram showing the structure of a frame used bythe digital modulator of the embodiment and waveforms of signals Rs, A1,A0, As, Bs and SF.

FIG. 3 is a block diagram showing the structure of an arithmetic circuitand a numerical control oscillator of the digital demodulator of theembodiment.

FIGS. 4(A) and 4(B) are a diagram illustrating a superframeidentification pattern in a frame of a signal supplied to the digitaldemodulator of the embodiment.

FIGS. 5(A) and 5(B) are a phase error table used by the digitaldemodulator of the embodiment.

EMBODIMENT OF THE INVENTION

An embodiment of a digital demodulator according to the invention willbe described.

FIG. 1 is a block diagram showing the structure of the digitaldemodulator of the embodiment.

Prior to describing the digital demodulator according to the embodimentof the invention, the structure of a frame used by the hierarchicaltransmission system will be described. FIG. 2(a) is a diagram showing anexample of the frame structure used by the hierarchical transmissionsystem. One frame is constituted of one header of 192 symbols and aplurality of pairs of 203 symbols and 4 symbols, totaling in 39936symbols.

More specifically, one frame is constituted of: a frame sync pattern(BPSK) of 32 symbols (of 32 symbols, front 20 symbols are used); atransmission and multiplexing configuration control (TMCC) pattern(BPSK) of 128 symbols for transmission multiplexing configurationidentification; a superframe identification information pattern of 32symbols (of 32 symbols, front 20 symbols are used); a main signal(TC8PSK) of 203 symbols and a burst symbol signal of 4 symbols(indicated by BS in FIG. 2(a)) to be BPSK modulated by a pseudo-randomsignal set per each frame period; a main signal (TC8PSK) of 203 symbolsand a burst symbol signal of 4 symbols; a main signal (QPSK) of 203symbols and a burst symbol signal of 4 symbols; and a main signal (BPSK)of 203 symbols and a burst symbol signal of 4 symbols, respectivelyarranged in this order 8 frames are called a superframe and thesuperframe identification information pattern is used for identifyingthe superframe.

Referring back to FIG. 1, the digital demodulator according to theembodiment of the invention will be described. The digital modulator ofthe embodiment has an arithmetic circuit 1, a numerical controloscillator 2, a roll-off filer 3 made of a digital filter having theraised cosine characteristics, a frame sync timing circuit 4, atransmission mode judging circuit 5, an inversion command signalgenerator circuit 6 for generating an inversion command signal of “0” or“1” in accordance with a BPSK signal having a known pattern; an invertercircuit 7 for inverting the demodulated baseband signals ID and QD atthe same time when necessary, in response to the inversion commandsignal output from the inversion command signal generator circuit 6; acarrier reproduction phase error detector circuit 8 having a carrierreproduction phase error table with a phase converging point at theabsolute phase; a carrier filter 9 of a low-pass digital filter, an AFCcircuit 10, and an AND circuit 11 for controlling the operation of thecarrier filter 9.

As shown in FIG. 3, the numerical control oscillator 2 has a sine table23 for outputting sine data 23 a and 23 b of opposite polarities and acosine table 24 for outputting cosine data 24 a and 24 b. In accordancewith the output from the AFC circuit 10, the numerical controloscillator 2 outputs the sine data 23 a and 23 b and cosine data 24 aand 24 b of opposite polarities, to output sine and cosine signals ofopposite polarities which substantially form reproduction carriers incooperation with the AFC circuit 10.

The arithmetic circuit 1 has as shown in FIG. 3: a multiplier 1 a formultiplying a quasi-sync detected 1 axis baseband signal i by the sinedata 23 a; a multiplier 1 b for multiplying the baseband signal i by thecosine data 24 a; a multiplier 1 d for multiplying a quasi-sync detectedQ axis baseband signal q by the opposite polarity sine data 23 b; amultiplier 1 e for multiplying the baseband signal q by the cosine data24 b; an adder 1 c for adding outputs of the multipliers 1 b and 1 d andoutputting the addition result as a baseband signal 1; and an adder Iffor adding outputs of the multipliers 1 a and 1 e and QPSK signalsection, a signal As shown in FIG. 2(E) which takes the high levelduring the frame sync pattern section, a signal Bs shown in FIG. 2(F)which takes the high level during the burst symbol signal section, and asignal SF shown in FIG. 2(G) which takes the high level during thesuperframe identification pattern section.

Next, the superframe identification pattern will be described. FIG. 4(A)is a diagram showing the superframe identification pattern. W₁represents the frame sync pattern, and takes the same pattern for allframes. In FIGS. 4(A) and 4(B), patterns W₂ and W₃ represent thesuperframe identification patterns including the frame sync pattern andsuperframe identification pattern extracted from each frame. The patternW₂ is used as the superframe identification pattern for the first frame,and the pattern W₃ is used as the superframe identification pattern forall seven other frames from the second to eighth frames. The pattern W₃is an inverse pattern of the pattern W₂.

The frame sync timing circuit 4 outputs a superframe identificationpattern identification signal which identifies the superframeidentification pattern taking the low level during the section of thesuperframe identification pattern W₂ of the start frame shown in FIG.4(B) and the high level during the section of the superframeidentification pattern W₃ of the following seven frames.

The inversion command signal generator circuit 6 has a frame syncpattern generator circuit 61, a superframe identification patternoutputting the addition result as a baseband signal Q. The arithmeticcircuit 1 therefore tunes the frequencies of the baseband signals i andq and outputs the frequency tuned baseband signals i and Q to theroll-off filter 3.

Upon reception of baseband signals ID and QD output from the roll-offfilter 3, the frame sync timing circuit 4 outputs a TMCC pattern to thetransmission mode judging circuit 5. In accordance with the decodedresult of the TMCC pattern, the transmission mode judging circuit 5supplies the frame sync timing circuit 4 with a 2-bit transmission modesignal representing a high hierarchical 8PSK signal (demodulated fromthe 8PSK modulated signal); a low hierarchical QPSK signal (demodulatedfrom the QPSK modulated signal); and a low hierarchical BPSK signal(demodulated from the BPSK modulated signal).

The frame sync timing circuit 4 receives the baseband signals ID and QDto detect a sync pattern and output a frame sync signal FSYNC to the AFCcircuit 10 which executes an AFC operation for each frame, and alsoreceives the transmission mode signal from the transmission mode judgingcircuit 5 to output: a signal Rs shown in FIG. 2(B) which synchronizeswith the start of the frame sync pattern;

a signal A1 shown in FIG. 2(C) which takes a high level during the BPSKsignal section; a signal A0 shown in FIG. 2(D) which takes the highlevel during a frame sync pattern section, a superframe identificationpattern section, a burst symbol signal section and a generator circuit62, a burst symbol pattern generator circuit 63, an exclusive OR circuit64, and an OR gate circuit 65 which outputs the inversion commandsignal.

The frame sync pattern generator circuit 61 is reset by the signal Rsand receives as the enable signal the signal As, i.e., the signal outputduring the frame sync pattern section. Synchronously with a bit clocksignal, the frame sync pattern generator circuit 61 sequentially outputsvia the OR gate circuit 65 the signal constituting the frame syncpattern as the inversion command signal. For example, the inversioncommand signal takes a bit “1” to enable the inversion command.

The superframe identification pattern generator circuit 62 is reset bythe signal Rs and receives as the enable signal the signal SF, i.e., thesignal output during the superframe identification pattern section.Synchronously with the bit clock signal, the superframe sync patterngenerator circuit 62 sequentially outputs the superframe identificationpattern W₂ constituting the start frame to the exclusive OR circuit 64.The pattern W₂ is subjected to the exclusive OR operation with thesuperframe identification pattern identification signal output from theframe sync timing circuit 4 and the result is supplied to the OR gatecircuit 65. In accordance with the superframe identification patternidentification signal, the exclusive OR circuit 64 outputs thesuperframe identification pattern W₂ for the start frame, and thepattern W₃ inverted from the pattern W₂ for the following seven frames.Therefore, the exclusive OR circuit 64 outputs the superframeidentification pattern signals W₂, W₃, W₃, W₃, W₃, W₃, W₃, and W₃ shownin FIG. 4(A) for the frames from the start to eighth frames via the ORgate circuit 65 as the inversion command signals. For example, theinversion command signal takes a bit “1” to enable the inversioncommand.

The burst symbol pattern generator circuit 63 is reset by the signal Rsand receives as the enable signal the signal Bs, i.e., the signal outputduring the burst symbol pattern section. Synchronously with the bitclock signal, the burst symbol generator circuit 63 sequentially outputsvia the OR gate circuit 65 the burst symbol signal as the inversioncommand signal. The burst symbol pattern generator circuit 63 thereforeoutputs the burst symbol signal as the inversion command signal. Forexample, the inversion command signal takes a bit “1” to enable theinversion command.

Therefore, the inversion command signal generator circuit 6 outputs theframe sync pattern signal as the inversion command signal “1” during theframe sync pattern section, outputs as the inversion command signal thesignal “1” of the signal shown in FIG. 4(A) corresponding to each frameduring the superframe identification pattern section, and outputs as theinversion command signal the burst symbol signal “1” during the burstsymbol pattern section.

In accordance with the inversion command signal output from theinversion command signal generator circuit 6, the inverter circuit 7inverts the baseband signals ID and QD output from the roll-off filer 3at the same time when necessary. More specifically, when the inversioncommand signal takes the low level, the baseband signals ID and QD aredirectly sent to the carrier reproduction phase error detector circuit8, whereas when the inversion command signal takes the high level, thebaseband signals ID and QD are inverted at the same time and sent to thecarrier reproduction phase error detector circuit 8.

Upon reception of the baseband signals ID and QD via the invertercircuit 7, the carrier reproduction phase error detector circuit 8detects a phase error between the phase calculated from the signal pointof the baseband signals ID and QD and the absolute phase to therebyoutput a phase error voltage corresponding to the phase error.

More specifically, the carrier reproduction phase error detector circuit8 has a carrier reproduction phase error table shown in FIG. 5(A) withthe phase converging point (0 (2π) radian) of the absolute phase. Thephase is obtained from the signal point of the baseband signals ID andQD supplied from the inverter circuit 7, and the phase error voltagecorresponding to the phase is obtained from the carrier reproductionphase error table and supplied to the carrier filter 9.

The reference point of the phase of the signal point of the basebandsignals ID and QD output from the roll-off filter is either 0 (2π)radian or π radian. However, if the signal output from the inversioncommand signal generator circuit 6 as the inversion command signalduring the frame sync pattern section, superframe identification patternsection or burst symbol section takes the high level, the basebandsignals ID and QD output from the roll-off filter 3 are inverted at thesame time and the reference point of the phase of the signal point ofthe inverted baseband signals ID and QD is 0 (2π) radian. Conversely, ifthe signal output from the inversion command signal generator circuit 6as the inversion command signal during the frame sync pattern section,superframe identification pattern section or burst symbol section takesthe low level, the baseband signals ID and QD output from the roll-offfilter 3 are not inverted but are directly output from the invertercircuit 7 and the reference point of the phase of the signal point ofthe inverted baseband signals ID and QD is 0 (2π) radian.

Therefore, the reference point of the phase obtained from the signalpoint of the baseband signals ID and QD input to the carrierreproduction phase error detector circuit is 0 (2π) radian, so that thephase error can be detected from the carrier reproduction phase errortable shown in FIGS. 5(A) and 5(B).

If the phase obtained from the signal point of the baseband signals IDand QD input from the inverter circuit 7 has a phase in the increasedirection from π radian or larger to 0 (2π) radian, a negative phaseerror voltage shown in FIGS. 5(A) and 5(B) is output, whereas if thephase has a phase in the decrease direction from smaller than π radianto 0 (2π) radian, a positive phase error voltage shown in FIGS. 5(A) and5(B) is output. This phase error voltage is supplied to the AFC circuit10. Under the control of the AFC circuit 10, the phase obtained from thesignal point is converged to 0 (2πL) as shown in FIG. 5(B). In thiscase, the phase error voltage takes a plus direction maximum value orminus direction maximum value at the phase of π radian.

The phase error voltage corresponding to the phase obtained from thesignal point of the baseband signals ID and QD and output from thecarrier reproduction phase error detector circuit 8 is supplied to thecarrier filer 9 of the digital low-pass filter and smoothed. In the caseof the minus direction, the signal obtained through the logical AND ofthe signals A1 and A0 by the AND circuit 11 is supplied as a carrierfilter control signal (CRFLGP), and the carrier filer 9 executes afiltering operation only during the frame sync pattern section,superframe identification pattern section and burst symbol signalsection. During the BPSK signal section, QPSK signal section and 8PSKsignal section of the main signals, the low level signal is output fromthe AND circuit 11 to stop the filtering operation of the carrier filter9. Therefore, the output of the carrier filter 9 is maintained at theoutput immediately before the filtering operation is stopped. The outputof the carrier filer 9 is supplied as a tuning voltage to the AFCcircuit 10.

As the baseband signals of the main signals during the BPSK signalsection, QPSK signal section and 8PSK signal section are supplied to thecarrier reproduction phase error detector circuit 8, the phase errorvoltage is detected from the carrier reproduction phase error table(refer to FIGS. 5(A) and 5(B)) having the reference point of 0 (2π)radian. However, in this case, the carrier filter 9 is disabled so thatany practical problem will not occur.

The operation of the digital demodulator constructed as above accordingto the embodiment of the invention will be described.

In a BS digital broadcasting receiver, generally, a desired signal in adesignated channel is scanned by the AFC circuit 10 to capture thecarrier. In the digital demodulator according to the embodiment of theinvention, upon reception of a desired signal, the baseband signals Iand Q orthogonally demodulated by the quasi-detection method aresupplied to the arithmetic circuit 1 which calculates the basebandsignals I and Q by using the output data from the numerical controloscillator 2 and converts the signals I and Q into the baseband signalsI and Q.

The baseband signals I and Q are supplied to the roll-off filter 3 whichoutputs the baseband signals ID and QD. The baseband signals ID and QDare supplied via the inverter circuit 7 to the carrier reproductionphase error detector circuit 8 which obtains the carrier reproductionphase error voltage in accordance with the phase corresponding to thesignal point of the baseband signals ID and QD supplied via the invertercircuit 7. The phase error voltage is smoothed by the carrier filter 9and supplied as the tuning voltage to the AFC circuit 10. An output ofthe AFC circuit 10 is supplied to the numerical control oscillator 2 toreproduce the carrier by controlling the carrier frequency to make thephase error voltage become zero.

The baseband signals ID and QD are also supplied to the frame synctiming circuit 4 which detects the frame sync pattern to capture theframe sync and establish the frame timing. The time sequential positionsof the frame sync pattern, TMCC pattern, superframe identificationpattern and burst symbol signals are therefore identified. The TMCCpattern is sent to the transmission mode judging circuit 5 and decoded.Upon reception of the transmission mode signal output from thetransmission mode judging circuit 5, the frame sync timing circuit 4outputs the signals Rs, A1, A0, As, Bs and SF.

Upon reception of the signals Rs, As, Bs and SF and superframeidentification pattern identification signal sent from the frame synctiming circuit 4, the inversion command signal generator circuit 6identifies the reception phase points at respective timings from thephases and timings of the frame sync pattern signal, superframeidentification pattern signal and burst symbol signal, and outputs theinversion command signals having the high or low level to be determinedfrom the reception phase point, to the inverter circuit 7.

Upon reception of the inversion command signal, the inversion circuit 7supplies the baseband signals ID and QD without inverting them to thecarrier reproduction phase error detector circuit 8 if the inversioncommand signal has the low level, whereas it supplies the basebandsignals ID and QD by inverting them to the carrier reproduction phaseerror detector circuit 8 if the inversion command signal has the highlevel. In this manner, the reference phase of the phase obtained fromthe signal point of the baseband signals ID and QD output from theinverter circuit 7 is fixed to 0 (2π) radian and thereafter the basebandsignals ID and QD are supplied to the carrier reproduction phase errordetector circuit 8.

In the carrier reproduction phase error detector circuit 8 which aresupplied with the baseband signals ID and QD from the inverter circuit7, the phase error voltage corresponding to the phase obtained from thesignal point of the baseband signals ID and QD and the converging pointof 0 (2π) of the phase error table shown in FIGS. 5(A) and 5(B) isobtained and supplied to the carrier filter 9.

In this case, the logical AND output of the signals A1 and A0, i.e., thesignal having the high level during the frame sync pattern section,superframe identification pattern section and burst symbol signalsection, is output as the carrier filter control signal (CRFLGP). Duringthe period while the carrier filter control signal (CRFLGP) takes thehigh level, the phase error voltage is smoothed by the carrier filer 9whose output is supplied to the AFC circuit 10. The AFC circuit 10controls the frequency of the carrier in accordance with the output ofthe carrier filer 9 to thereby perform carrier reproduction throughburst signal reception.

During the BPSK signal section, QPSK signal section and 8PSK signalsection of the main signals, the carrier filter control signal (CRFLGP)takes the low level. During the period while the carrier filter controlsignal (CRFLGP) takes the low level, the filtering operation stops andan output of the carrier filter 9 is maintained at the outputimmediately before the filtering operation stops to thereafter executecarrier reproduction.

As described above, in the digital demodulator of the embodiment, thecarrier reproduction is performed in accordance with the phase errorvoltage obtained from the phase error table having one converging point.Therefore, the phase point of the reception signal is converted into onephase point and the reception signal is subjected to the absolutephasing. It is therefore unnecessary to use an absolute phasing circuit.The necessary area for an integrated digital demodulator can be reduced.

As the baseband signals of the main signals during the BPSK signalsection, QPSK signal section and 8PSK signal section are supplied to thecarrier reproduction phase error detector circuit 8, the phase errorvoltage is detected from the carrier reproduction phase error tablehaving the reference point of 0 (2π) (refer to FIGS. 5(A) and 5(B)).However, in this case, the carrier filter 9 is disabled so that anypractical problem will not occur as described earlier. Data may beoutput as a portion of the burst signal. In this case, the section notoutputting the data is used.

In this embodiment, the demodulated baseband signals ID and QD areinverted at the same time when necessary by the inverter circuit 7 inaccordance with the inversion command signal. Instead, the carrierreproduction phase error detector circuit may be provided with the phaseerror table shown in FIGS. 5(A) and 5(B) and a phase error table havingthe phase converging point of π radian. In this case, the invertercircuit 7 can be omitted by selecting either the phase error table shownin FIGS. 5(A) and 5(B) or the phase error table having the phaseconverging point of π radian, in accordance with the inversion commandsignal “0” or “1”.

INDUSTRIAL APPLICABILITY

As described above, according to the digital demodulator of thisinvention, the carrier reproduction is performed in accordance with thephase error corresponding to the phase of the reception signal detectedby using the phase error table having one converging point, during theperiod while a signal having a known pattern is received. Therefore, thereception signal can be subjected to the absolute phasing, an absolutephasing circuit is unnecessary, and the necessary area for an integrateddigital demodulator can be reduced.

What is claimed is:
 1. A digital demodulator for a digital broadcastingreceiver for receiving digital modulated waves multiplexed in the timeaxis by a plurality of modulation methods, comprising: inverter meansfor selectively inverting demodulated baseband signals in accordancewith a BPSK signal having a known pattern prepared in advance; andcarrier reproduction phase error detector means provided with a phaseerror table having a phase converging point as an absolute phase, saidcarrier reproduction phase error detector means outputting a phase errorsignal corresponding to a phase difference between a phase obtained froma signal point of the demodulated baseband signals output from saidinverter means and a phase of the phase converging point, whereincarrier reproduction is executed by controlling a frequency of areproduction carrier so as to make the phase of the signal point becomecoincident with the phase converging point.
 2. A digital demodulatoraccording to claim 1, further comprising a carrier filter of a low-passfilter, said carrier filter being input with the phase error signal fromsaid carrier reproduction phase error detector means and stopping afiltering operation during a BPSK signal section, a QPSK signal sectionand an 8PSK signal section of main signals, and the carrier reproductionbeing executed in accordance with an output of said carrier filter.